EE524/CptS561 Advanced Computer Architecture 654321654321 321321 3 2AM()-M()M[R3] 1 DMult1M[R3]2 M M[R3] F4 1 FP adders FP Multipliers Common data bus (CDB) Reservation Stations From memory Load buffers FP operation queue From instruction unit FP Registers To memory Store buffers Operation bus Operand buses Cycle: 11 ADD F6,F8,F2 DIVD F10,F0,F6 MULTD F0,F2,F4 F6: add2 F0 : mult1 F10: mult2 Add2: (M()-M())+M() F6  (M()-m())+M()
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