Slide - 168 Gated Clocks Can lead to both functional and timing problems –Clock behavior subject to both synthesis and placement & routing –Can be a s
{"Image DocumentName": "Gated Clocks Can lead to both functional and timing problems", "Image ImageDescription": "Clock behavior subject to both synthesis and placement & routing. Can be a source of additional clock skew. Glitches on clock path possible. Recommendations: Use clock enables for clock gating functionality. Use dedicated device resources (e.g. clock control blocks) to gate clocks synchronously and reduce power. If you must build your own gating logic. Use a synchronous gating structure. Ensure global clock routing is used for clock signal. Gate the clock at the source.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}