Fig. 1. Schematic view of the studied Si0.45Ge0.55 channel devices shows an HfO2/SiO2 high-k gate stack together with a thin Si cap spacer on top of the strained SiGe layer. In this paper, nanoscale and large-area devices with two different Si cap layer thicknesses of dSiCap = 0.65 nm and dSiCap = 2 nm and a reference Si transistor are studied in detail.
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