MultiClock Cycle Design Instruction Content Depended Phases – Phase 3 (continued) Branch completion Branch (beq) –if (A == B) PC = ALUOut; – equal compare reg A & B, if equal, set Zero output of ALU which means branch successful –ALUSrcA set to 1 ALUSrcB set to 00 ALUOp set to 01 (subtract) PCWriteCond asserted PCSource set to 01 /* PC taken from ALUOut */ PCWrite de-asserted (by default) – prevents beq address from being set when unsuccessful branch - ALU zero output must be set to use beq address.
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