SoC design with GALS Most IPs are synchronous Different components may have different operating frequencies Some components have variable latencies (e.g., cache hit/miss latency) Multiple clock domains are essential EMicro 2013Elastic circuits86 BridgeBridge CDCCDC DSPDSP PPPP PPPP Fast Bus Slow Bus BridgeBridge CDCCDCMemMem CLK2 CLK1 CLK3
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