ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits9 Key Design Differences Synchronous logic design: –proceeds without taking timing correctness (hazards, signal ack-ing etc.) into account –Combinational logic and memory latches (registers) are built separately –Static timing analysis of CL is sufficient to determine the Max Delay (clock period) –Fixed set-up and hold conditions for latches
{}