Conditional capture flip-flop
{"Image DocumentName": "Conditional capture flip-flop", "Image ImageDescription": "First stage: pulse generator with internal clock gating. When Clk=1, S=R=1. When Clk=1, Clk1=0, S can switch low if D=1, Q=0, R can switch low if D=0, Q=1. Otherwise, S=R=1 \uf0ae no energy consumption. Second stage: pass-gate implementation of M-SAFF latch (Oklobdzija, Stojanovic) No setup time degradation due to clock gating. (Kong et al. 2000), Copyright \u00a9 2000 IEEE. Nov. 14, 2003.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}