Industrial Imaging Interface Portfolio : Plug-and-Go! Devices
{"Image DocumentName": "Industrial Imaging Interface Portfolio : Plug-and-Go! Devices", "Image ImageDescription": "Basic Application Requirement. Other System Requirements. Family. Data Throughput. Max Cable Reach  Data Type. FPGA-Link to Gbps. 40m of 1.25 Gbps. 20m of Gbps. ANY. Redundancy & Daisy chaining. FPGA friendly, LVDS parallel interface. Low system BOM, design time. FPD-Link to 2700 Mbps. 4m to 8m of 2 Gbps. 10/16/18/24/32 bit data interface. Lock to random data, low EMI. FPGA/ASIC as logic interconnect. Channel Link (Camera- Link) 500 to 5000 Mbps. 4m to 8m of MDR cable at 2.5 Gbps. 21/28/48 wide bus interface. Transcript: Also, from the standpoint of the product families, the new product families, the first one is the FPGA-Link product that goes from 1.25 gigabits per second to gigabits per second, and can go a maximum reach of 40 meters on a CAT-6 at 1.25 gigabits per second. If you run at a higher bandwidth, of course, it goes a shorter distance to 20 meters. But these systems are redundant, they support daisy chaining, they re FPGA-friendly. They have an LVDS and parallel interface. And, so it provides a lower system BOM and quick design time. The next family is the FPD-Link 2 family, and that s 120 to 2700 megabits per second, and that s 4 meters to 8 meters of CAT-6 at that 2 gigabit per second speed. And this provides a larger data bit interface from 10 bits all the way up to 32-bit data, depending on the family, and it will lock to random data. It has a low EMI and connects directly with the FPGA or ASIC as we were talking about working very closely. The older product family that is being used in a number of machine vision systems today is the Channel Link family, and that is also called Camera Link. For those systems, it s 500 to 5,000 megabits per second, and the distance you get for those is from 4 meters to 8 meters, and that supports a bus from 21 bits to 48 bits. And one important thing to see there is that these systems allow you to have plug-and-go seamless video. So on the bottom of your screen, you ll see the headers. Using the SerDes, you can remove those headers and have all of your bandwidth going towards data. HAROLD JOSEPH: Now there was a demo that was done. I think it s part of like a podcast or whatever, right? And did it address one of these particular products? ALEX TAN: That s right. It was on the FPGA Link family of products. HAROLD JOSEPH: Okay, and that was an actual demo and that s online too. That was done as part of our newsletter I think. ALEX TAN: Yes, absolutely. HAROLD JOSEPH: Okay. Author\u2019s Original Notes: FPGA-Link : DS32EL0421/0124, DS32ELX0421/0124. FPD-Link 2 : DS90UR241/124, DS92LV3241/42 , DS92LV2421/2421  Channel-Link : DS90CR285/286, DS90CR287/288.   Cable length is for reference only, various system conditions impact the maximum reach. National 3.0 Conference. Alex Chin, Harold Joseph, Dave Lewis, Wanda Garrett, Ken Filliter, Sanjay Gajendra, Cornel Pazara, Kristen Elserougi, Stephen Ott.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}