FET Selection: AC LossPswAC = ½ * Vdsoff * Idson * (trise + tfall)/Tsw. High Freq = High Loss. Low Freq = Low Loss.
{"Image DocumentName": "FET Selection: AC LossPswAC = \u00bd   Vdsoff   Idson   (trise + tfall)/Tsw. High Freq = High Loss. Low Freq = Low Loss.", "Image ImageDescription": "Regions of power loss (V I) Vsw. Miller Plateau. Miller Plateau. Vdriver. The % of the switching period that is spent in the transition regions is greater for higher switching frequencies. Thus, higher switching frequency means greater AC switching loss as is shown in the diagram in the upper left. Lowering the switching frequency lowers the losses as is shown in the upper right. AN-1628 has more details on this (http://www.national.com/an/AN/AN-1628.pdf). Vth. Vth. Isw. Vg. Vsw = -Vds. Switch Off. On. Off. Trise. Tfall.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}