Simple CMOS Circuits: The D Register (D Flip-Flop)
{"Image DocumentName": "Simple CMOS Circuits: The D Register (D Flip-Flop)", "Image ImageDescription": "D Latch. -QM. D Latch. D. C. C. Q. CLK. Circuit Schematic: Comprised of two D latches tied in series with input D, output Q, and CLK control line. Each D latch is simply constructed out of two inverters cross coupled with a X-gate in the feedback loop and having a second X-gate in series with the input. Each X-gate switch C is closed if its control input is high (Vdd) and open if its control is low. Single clock fed directly (true) to 2nd latch (slave) and inverted to 1st latch (master). Operation: (positive edge triggered) When CLK goes to zero, master latch is opened to input D (feedback loop is disabled), while slave latch holds previous data and is closed to signal at node QM. When CLK goes to Vdd, master latch is isolated from input D (& feedback loop enabled) to hold data, while slave latch opens to receive data from master giving valid Q output. R. W. Knepper. SC571, page 1-16.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}