AXI is an Interface Specification Processor Peripherals PLB46 Arbiter AXI Slaves Interconnect AXI Shared Access Bus AXI Interconnect IP Implementation
{"Image DocumentName": "AXI is an Interface Specification", "Image ImageDescription": "PLB46. Shared Access Bus. Processor. Interconnect. PLB. AXI Slaves. AXI Masters. AXI. AXI. AXI. AXI. Peripherals. AXI Interconnect IP. Implementation is not described in the spec. Several companies build and sell AXI interconnect IP Xilinx is building its own. PLB. Because AXI does not define the interconnect, it is possible that the interconnect could be specified as a shared bus. In such a case, AXI and PLBv46 implementations would share some common operational properties. AXI. AXI. AXI. AXI. PLB. AXI. AXI. PLB. Arrows indicate master/slave relationship, not direction of dataflow. Master. Slave. AXI is an interface specification, not a bus specification. Arbiter.", "Image XResolution": "37", "Image YResolution": "37", "Image ResolutionUnit": "Pixels/Centimeter", "Image Software": "SlidePlayer", "Image YCbCrPositioning": "Centered"}