S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Tbl 4.13 Concrete RTN and Control Sequence for 2-bus SRC add Note the appearance of Grc to gate the output of the register rc onto the B bus and Sra to select ra to receive data strobed from the A bus Two register select decoders will be needed Transparent latches will be required for MA at step T0 StepConcrete RTNControl Sequence T0.MA  PC;PC out, C=B, MA in, Read T1.PC  PC + 4: MD  M[MA];PC out, Inc4, PC in, Wait T2.IR  MD;MD out, C=B, IR in T3.A  R[rb];Grb, R out, C=B, A in T4.R[ra]  A + R[rc];Grc, R out, ADD, Sra, R in, End
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